1. Field of the Invention
The present invention generally relates to a method and apparatus to electrically qualify high speed printed circuit board (PCB) connectors, and more specifically to a method and apparatus for evaluating quality of a PCB connector by testing parasitic effects through its common mode noise generation.
2. Description of the Related Art
With the ever increasing frequencies of operation, high speed PCB designs are becoming more and more challenging. Signal integrity issues like conductor loss, material loss, reflections, and crosstalk are becoming ever more important. PCB connectors are one such source causing signal integrity problems in these high speed systems. Connectors with proper pin assignment can minimize reflections, crosstalk and other parasitic effects, but they cannot totally remove these effects. That is the reason that high speed connectors that minimize signal integrity effects are very expensive.
One common problem that PCB electrical designers encounter regularly on their products is how to qualify a connector (also second source connector) for a particular design. It is especially tough to qualify when the design(s) is close to margin. Currently, equipment like a time-domain reflectometer (TDR) and a vector network analyzer (VNA) is used to extract loss and crosstalk profiles of connectors. Although these techniques seem adequate, these approaches depend on factors like good calibration, expensive instruments, and expensive cables. Any measurement without proper calibration or good cables would result in inferior results. Also, the learning curve involved with these techniques is very steep.